The present invention relates generally to integrated circuits, and more particularly, to a programmable clock divider circuit.
Integrated circuits having various modules are widely used in computer systems for performing various functions. Examples of circuit modules include processors, logic gates, flip-flops, latches, system busses, and so forth. These circuit modules are often referred to as functional circuits and are driven by a clock signal. Depending on the system requirements, different functional circuits may require different clock signals (having different frequencies) for their operation. For example, an integrated circuit may include one set of functional circuits that operates in a first clock domain and another set that operates in a second clock domain.
An integrated circuit may include multiple clock generators that generate clock signals having different frequencies. However, having multiple clock generators occupies large area, therefore, it is preferable to have a system that includes a single clock generator that generates an input clock signal and one or more clock dividers that divide the input clock signal to generate divided clock signals. A typical clock divider receives an input signal having a frequency fin and generates an output signal having a frequency fout=fin/n, where n is a frequency ratio. A programmable clock divider is a type of clock divider that can be programmed to divide an input clock signal using a range of frequency ratios.
FIG. 1 shows a conventional programmable clock divider 100 that receives an input clock signal CLK_IN and generates a divided clock signal CLK_OUT. The programmable clock divider 100 includes an adder 102, a down counter 104, first and second comparators 106 and 108, an active-low latch 110, and a multiplexer or mux 112. The adder 102 is provided with a frequency ratio N−1 (externally) that is a ratio of the divided clock signal CLK_OUT and the input clock signal CLK_IN, and increments the frequency ratio N−1 by one to generate a ratio value N. The down counter 104 sets the frequency ratio N−1 as an initial count value and decrements the initial count value by one at every positive edge of the input clock signal CLK_IN to generate a count value. The first comparator 106 is connected to the adder 102 and the down counter 104 for receiving the ratio value N and count value respectively, and generating a first signal SIG_A based on a first comparison between the ratio value N and the count value. The first signal SIG_A is a pulse that has alternate logic high and low states. The first signal SIG_A is high when at least one of the conditions below is true:                (i) the ratio value N is even and the count value is greater than or equal to a first ratio value N/2, and        (ii) the ratio value N is odd, and the count value is greater than or equal to a second ratio value (N/2)+1.        
The second comparator 108 is connected to the adder 102 and the down counter 104 for receiving the ratio value N and count value respectively, and generating a second signal SIG_B based on a second comparison between the ratio value N and the count value. The second signal SIG_B also is a pulse signal that has alternate logic high and low states. The second signal SIG_B is high when at least one of the conditions below is true:                (i) N is even, and the count value is greater than or equal to the second ratio value (N/2)+1,        (ii) N is odd, and the count value is greater than or equal to a third ratio value ((N−1)/2)+1, and        (iii) N is odd and the count value is equal to zero.        
The active-low latch 110 delays the second signal SIG_B by a half cycle of the input clock signal CLK_IN to generate a delayed second signal SIG_C. The mux 112 has first and second input terminals for receiving the first signal SIG_A and the delayed second signal SIG_C, a select terminal for receiving the input clock signal CLK_IN, and an output terminal for generating the divided clock signal CLK_OUT. CLK_OUT is equal to the delayed second signal SIG_C when the input clock signal CLK_IN is high and is the first signal SIG_A when the input clock signal CLK_IN is low.
FIG. 2 is a timing diagram 200 illustrating the input clock signal CLK_IN, the first and second signals SIG_A and SIG_B, the delayed second signal SIG_C, and the divided clock signal CLK_OUT. The output of the first comparator 106, i.e., the first signal SIG_A is low from time T1 to T3, transitions from low to high at time T3, and transitions from high to low at time T7, based on the conditions discussed above. Similarly, the output of the second comparator 108, i.e., the second signal SIG_B transitions from low to high at time T1, i.e., at a positive edge of the input clock signal CLK_IN and transitions from high to low at time T7, i.e., at a positive edge of the input clock signal CLK_IN based on the conditions discussed above. The output of the active-low latch 110, i.e., the delayed second signal SIG_C transitions from low to high at time T2, i.e., at a negative edge of the input clock signal CLK_IN, and from high to low at time T8, i.e., at a negative edge of the input clock signal CLK_IN.
The mux 112 selects a portion of the first signal SIG_A (from time T1 to T2) as the divided clock signal CLK_OUT from time T2 to T3, a portion of the delayed second signal SIG_C (from time T2 to T3) as the divided clock signal CLK_OUT from time T3 to T4, and a portion of the first signal SIG_A (from time T3 to T4) as the divided clock signal CLK_OUT from time T4 to T5, and so on.
The portions of the first signal SIG_A that are selected by the mux 112 have a half clock cycle of the input clock signal CLK_IN to stabilize, as they are output by the mux 112 after a delay of a half clock cycle. Similarly, the portion of the second signal SIG_B that is selected by the mux 112 has one clock cycle to stabilize, as it is output by the mux 112 after a delay of one clock cycle.
During verification of timing paths of the clock divider 100, a half-cycle timing check is required to be performed for a first timing path from the down counter 104 to the mux 112 to verify if the first signal SIG_A stabilizes in the half clock cycle. Similarly, a full-cycle timing check is required to be performed for a second timing path from the down counter 104 to the mux 112 to verify the delayed second signal SIG_C. However, the combinational logic (i.e., the first comparator 106) that is a part of the first timing path, makes it difficult and cumbersome to perform the half-cycle timing check at high frequencies (in the order of Gigahertz) of the input clock signal CLK_IN. Further, as the size and complexity of the first comparator 106 increases, it becomes impossible to perform a half-cycle timing check in the first timing path, as a large number of circuits must be verified in a limited time period (in the order of 10−10 seconds).
One solution to tackle the above-mentioned problem is to add one or more clock buffers in the path of the input clock signal CLK_IN to delay the input clock signal CLK_IN. However, adding clock buffers increases overall power consumption and clock latency of the integrated circuit and increases on-chip variations (OCVs), which introduces a new set of challenges for clock balancing.
Therefore, it would be advantageous to have a programmable clock divider that supports a half-cycle timing check using high frequency input clock signals, does not require additional clock buffers to be added in the input clock signal path, and addresses the above-mentioned limitations of existing programmable clock dividers.